Reducing power dissipation is a key design goal for portable computing and communication devices that employ increasingly sophisticated and power-consuming signal processing techniques. Flexibility is another critical requirement that mandates the use of programmable components. However, there is a fundamental trade-off between efficiency and flexibility, and as a result, programmable designs incur significant performance and power penalties compared to application-specific integrated circuits (ASICs).
As the communications market continues its growth and rapid rate of change, equipment vendors struggle with the conflicting goals of performance, flexibility, cost and fast time-to-market. Traditional processing approaches such as digital signal processors (DSPs), ASICs, application-specific standard products (ASSPs) and field-programmable gate arrays (FPGAs) all force the designer to trade off between these key parameters. Thus, a new class of processor that enable designers to meet all these goals simultaneously is needed.
Future networked embedded devices, whether wired or wireless, will need to support multiple standards and protocols of communications and digital signal processing. This is due to convergence of voice, data and video, changing standards, and a high demand for evolving features. Equipment vendors are required to build systems that are more flexible and field upgradeable. For example, there is a strong demand for multi-protocol systems that can adapt to changing traffic patterns or support multiple markets. U.S. wireless infrastructure for example, must handle CDMA-One and TDMA digital traffic as well as the CDMA2000 standard. Since no one can accurately predict the volume of traffic of each type over the next few years, nor the final communication standard definitions, vendors strive to create flexible systems that can instantaneously adapt to changing patterns. Flexibility also allows vendors to differentiate their products and create higher value using proprietary algorithms. Reconfigurable systems have recently emerged as a promising implementation platform for such embedded computing by exhibiting both high performance [see, for example, G. R. Goslin, “A Guide to Using Field Programmable Gate Arrays for Application Specific Digital Signal Processing Performance”, Proceedings of SPIE, vol. 2914, p 321-331], and low power consumption [see, for example, A. Abnous et al, “Evaluation of a Low-Power Reconfigurable DSP Architecture”, Proceedings of the Reconfigurable Architecture Workshop, Orlando, Fla., USA, March 1998, and M. Goel and N. R. Shanbhag, “Low-Power Reconfigurable Signal Processing via Dynamic Algorithm Transformations (DAT)”, Proceedings of Asilomar Conference on Signals, Systems and Computers, Pacific Grove, Calif., November, 1998] frequently required by such system-on-a-chip designs. The current trend of reconfigurable architectures in both general purpose computing and embedded digital signal processing is to combine a programmable processor with reconfigurable computing components of different granularities (fine-grain [Digital Semiconductor, Digital Semiconductor SA-110 Microprocessor Technical Reference Manual, Digital Equipment Corporation, 1996, and TMS320C5x General-Purpose Applications User's Guide, Literature Number SPRU164, Texas Instruments, 1997], data-path [T. Anderson, The TMS320C2xx Sum-of-Products Methodology, Technical Application Re-port SPRA068, Texas Instruments, 1996] and mixed [T. Garverick et al, NAPA1000, http://www.national.com/appinfo/milaero/napa1000]). The problem of interface generation between hardware and software has recently gained attention by the VLSI CAD community. The problem of integrating processors with reconfigurable elements has added another dimension to the interface generation problem—between software and configware (configurable hardware). Careful configuration and interface code generation is essential [R. Razdan, K. Brace, M. D Smith, “PRISC software acceleration techniques”, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, Mass., USA, October 1994] to ensure that the overhead of reconfiguring will not offset the speed and energy savings of reconfigurable components. This need is especially pronounced when the reconfiguration frequency is large within an application and when the timing constraints on the application are tight—which is often the case for real-time DSP and communication applications.